Methods for forming semiconductor structures with differential surface layer thicknesses

ABSTRACT

A semiconductor structure having a substrate with a surface layer including strained silicon. The surface layer has a first region with a first thickness less than a second thickness of a second region. A gate dielectric layer is disposed over a portion of at least the first surface layer region.

FIELD OF THE INVENTION

The present invention relates generally to semiconductor structures andparticularly to semiconductor structures formed on strainedsemiconductor layers.

BACKGROUND

The recent development of silicon (Si) substrates with strained layershas increased the options available for design and fabrication offield-effect transistors (FETs). Enhanced performance of n-typemetal-oxide-semiconductor (NMOS) transistors has been demonstrated withheterojunction metal-oxide-semiconductor field effect transistors(MOSFETs) built on substrates having strained silicon and relaxedsilicon-germanium (SiGe) layers. Tensilely-strained silicon greatlyenhances electron mobilities. NMOS devices with strained silicon surfacechannels, therefore, have improved performance with higher switchingspeeds. Hole mobilities are enhanced in tensilely-strained silicon aswell, but to a lesser extent for strain levels less than approximately1.5%. Equivalent enhancement of p-type metal-oxide-semiconductor (PMOS)device performance, therefore, in such surface-channel devices presentsa challenge.

A structure that incorporates a compressively strained SiGe layer intandem with a tensilely strained Si layer can provide greatly enhancedelectron and hole mobilities. In this structure, electron transporttypically occurs within a surface tensilely strained Si channel and holetransport occurs within the compressively strained SiGe layer below theSi layer. To support the fabrication of NMOS transistors as well as PMOStransistors on this structure, the surface tensilely strained Si layerhas a typical thickness of 50-200 Ångstroms (Å) for providing a channelfor conduction of electrons. If this layer is thinner than 50 Å, thebeneficial mobility enhancement is significantly reduced because theelectrons are no longer completely confined within the strained Silayer. Although some NMOS devices are operational with a strainedsilicon surface channel of only 50 Å, even this strained silicon layerthickness may be too thick to allow modulation of p-type carriers in aburied SiGe layer by an operating voltage applied to the gate of a PMOStransistor.

Complementary metal-oxide silicon (CMOS) circuit design is simplified ifcarrier mobilities are enhanced equally for both NMOS and PMOS devices.In conventional silicon-based devices, electron mobilities areapproximately two times greater than hole mobilities. As noted, electronmobilities have been substantially increased with strained silicon.Methods for equally increasing hole and electron mobilities by formingdual-channel NMOS and PMOS devices on the same substrate areproblematic, in part because of different surface strained-siliconthickness requirements for the two types of devices.

SUMMARY

In a dual-channel CMOS structure, electron transport takes place in asurface channel, e.g., a strained silicon layer with a thickness greaterthan 5 nanometers (nm). Hole transport occurs either in a buriedchannel, such as a buried compressed SiGe channel, or in both thestrained silicon surface layer and the buried compressed SiGe layer.Hole mobility in this type of structure is improved because of areduction in hole scattering due to sub-band splitting, and because of areduction in hole effective mass, both of which are associated withtransport in strained SiGe and strained Si.

In a MOSFET, having carriers such as holes close to the gate improvesswitching speeds. A thinned strained silicon layer above a PMOS channelfacilitates control of hole transport by a voltage applied to a gateabove the PMOS channel. If the strained silicon layer over the PMOSchannel is too thick, the majority of carriers will be pulled closer tothe surface from the buried channel. This configuration will result in alack of device performance enhancement by the buried channel.Selectively thinning the strained silicon layer above a PMOS channelwhile maintaining a greater strained silicon thickness as an NMOSchannel enables better control of hole transport in p-channel deviceswhile simultaneously providing an adequate channel for electrontransport in n-channel devices.

In an aspect, the invention features a semiconductor structure having asurface layer having strained silicon disposed over a substrate, thesurface layer including a first region having a first thickness and asecond region having a second thickness, the first thickness being lessthan the second thickness. The structure also includes a gate dielectricdisposed over a portion of at least the first region of the surfacelayer.

One or more of the following features may also be included. The gatedielectric layer may be disposed over a portion of the second region ofthe surface layer. The gate dielectric layer thickness may beapproximately 10-100 Å. The first thickness may be approximately 7-20 Å.

In another aspect, the invention features a semiconductor structurehaving a surface layer with strained silicon disposed over a substrate.A portion of the surface layer has a minimum thickness necessary forgrowing a silicon dioxide layer having satisfactory integrity.

One or more of the following features may also be included. The minimumsurface layer thickness may be approximately 10-20 Å. The surface layermay be disposed over the underlying layer and the underlying layer mayinduce strain in the surface layer. The underlying layer may includegermanium and/or silicon. The underlying layer may be disposed over aninsulator layer.

In yet another aspect, a surface layer including strained silicon isdisposed over a substrate, the surface layer including a first regionhaving a first thickness and a second region having a second thickness,the first thickness being less than the second thickness. The firstregion has a first source and a first drain, with the first source andthe first drain including a first type of dopant. The second region hasa second source and a second drain, with the second source and thesecond drain including a second type of dopant.

One or more of the following features may also be included. The surfacelayer may include tensilely strained silicon. The first type of dopantmay be p-type and the second type of dopant may be n-type. The substratemay include a region under compressive strain sharing an interface withthe surface layer, the tensilely strained surface layer enhancingmobility of electrons and the compressively strained substrate regionenhancing mobility of holes. A gate may be disposed above the surfacelayer, with the first thickness being sufficiently small such thatapplication of an operating voltage to the gate modulates movement ofcharge carriers within the compressively strained substrate region, anda majority of the charge carriers populate the compressively strainedsubstrate region. An insulator may be provided between the gate and thesurface layer. The compressively strained substrate region may includesilicon and/or germanium.

In another aspect, the invention features a method for forming asemiconductor structure. The method includes providing a substratehaving a surface layer disposed thereon, the surface layer includingstrained silicon. A sacrificial layer is selectively formed in a portionof the surface layer. The sacrificial layer is selectively removed todefine a first region of the surface layer having a first thicknessproximate a second region of the surface layer having a secondthickness, with the first thickness being less than the secondthickness.

One or more of the following features may also be included. Prior toforming the sacrificial layer, a masking layer may be formed over thesurface layer, and a portion of the masking layer removed to expose theportion of the surface layer. The sacrificial layer may subsequently beselectively formed in the portion of the surface layer exposed by themasking layer. Forming the masking layer may include forming a maskingsilicon nitride layer. Forming the masking layer may also includeforming a pad silicon dioxide layer prior to forming the masking siliconnitride layer. A first source and a first drain may be formed in thefirst region of the surface layer, the first source and the first drainincluding a first type of dopant. A second source and a second drain maybe formed in the second region of the surface layer, the second sourceand the second drain including a second type of dopant. The first typeof dopant may be n-type and the second type of dopant may be p-type. Thesurface layer may be disposed over a relaxed layer. The relaxed layermay comprise germanium and/or silicon.

BRIEF DESCRIPTION OF DRAWINGS

FIGS. 1-8 are a series of schematic cross-sectional views of asemiconductor substrate illustrating a process for fabricating asemiconductor structure on the substrate; and

FIGS. 9-10 are schematic cross-sectional views of an alternativeembodiment of a semiconductor structure fabricated on a substrate.

Like referenced features identify common features in correspondingdrawings.

DETAILED DESCRIPTION

Referring to FIG. 1, which illustrates a structure amenable to use withthe present invention, a substrate 10 is made of a semiconductor, suchas silicon. Several layers collectively indicated at 11 are formed onsubstrate 10. In particular, a graded SiGe layer 12 is disposed oversubstrate 10. Graded SiGe layer 12 has a grading rate of, for example,10% Ge per micron of thickness, and a thickness T₁ of, for example, 2-5microns. A relaxed SiGe layer 14 is disposed over graded SiGe layer 12.Relaxed SiGe layer 14 contains, for example, 20-50% Ge and has athickness T₂ of, e.g., 0.2-2 microns. A compressed SiGe layer 16, undercompressive strain, is disposed over relaxed SiGe layer 14. CompressedSiGe layer 16 has a Ge content higher than the Ge content of relaxedSiGe layer 14. Compressed SiGe layer 16 contains, for example, 40-100%Ge and has a thickness T₃ of, e.g., 10-200 Ångstroms (Å). In anembodiment, compressed SiGe layer 16 thickness T₃ is approximately 100Å. A tensilely strained silicon surface layer 18 is disposed overcompressed SiGe layer 16, sharing an interface 19 with compressed SiGelayer 16. Strained silicon surface layer 18 has a starting thickness T₄of, for example, 50-300 Å. In an embodiment, starting thickness T₄ isapproximately 200 Å. A suitable substrate 10 with layers 11 can bereadily obtained from, e.g., IQE Silicon Compounds, Ltd., UK.

Referring to FIG. 2, a first masking layer 20, such as a pad silicondioxide layer, hereinafter referred to as pad oxide 20, is depositedover strained silicon surface layer 18 by a deposition method such aslow-pressure chemical vapor deposition (LPCVD). Pad oxide 20 has athickness T₅ of, e.g., 100 Å. Subsequently, a second masking layer 22,such as a masking silicon nitride layer, hereinafter referred to asmasking nitride 22, is deposited over pad oxide 20 by a depositionmethod such as plasma enhanced chemical vapor deposition (PECVD).Masking nitride 22 has a thickness T₆ of, for example, 500-1000 Å.

Referring to FIG. 3, a photoresist layer is deposited over a top surface24 of masking nitride 22 and patterned to form a photoresist mask 26.Photoresist mask 26 exposes top surface 24 of a first portion 28 ofmasking nitride 22 disposed over a first region 30 of substrate 10 andlayers 11. A device such as a PMOS transistor will be formed in firstregion 30 with subsequent processing (see, e.g., PMOS transistor 59 inFIG. 8). Photoresist mask 26 covers top surface 24 of a second portion32 of masking nitride 22 disposed over a second region 34 of substrate10 and layers 11, including strained silicon surface layer 18. A device,such as an NMOS transistor, will be formed in second region 34 withsubsequent processing (see, e.g., NMOS transistor 64 in FIG. 8).

Referring to FIG. 3 and also to FIG. 4, first masking nitride portion 28and a first portion 38 of pad oxide 20 underneath first masking nitrideportion 28 are both removed, leaving behind second masking nitrideportion 32 and a second portion 40 of pad oxide 20 that are protected byphotoresist mask 26. Specifically, exposed first masking nitride portion28 may be removed by a removal process such as a reactive ion etch (RIE)using gases such as a combination of nitrogen trifluoride, ammonia, andoxygen, or a combination of hydrogen bromide, chlorine, and oxygen.First pad oxide portion 38 may be removed by a wet etch that isselective to silicon, such as a hydrofluoric acid etch. The removal ofpad oxide portion 38 exposes a portion 41 of strained silicon surfacelayer 18. Ions are introduced into areas not covered by photoresist mask26, including first region 30, to form a well 36, defined, for purposesof illustration, by the boundary 36 b. For example, n-type ions, such asphosphorus, are implanted to form well 36 for a PMOS transistor. Thedosage and energy of the phosphorus ion implantation is, for example,400 keV with 1.5×10¹³ atoms/cm². After the selective removal of firstportions 28, 38 of masking nitride 22 and pad oxide 20 and the formationof well 36, photoresist mask 26 is removed by a stripping process suchas a dry strip in an oxygen plasma.

Referring to FIG. 5, a sacrificial layer 44 is formed on portion 41 ofstrained silicon surface layer 18. Sacrificial layer 44 is, for example,silicon dioxide grown by thermal oxidation. Thermal oxidation parametersmay include, for example, an oxygen ambient at atmospheric pressure at900° C. for 30 minutes. In an alternative embodiment, sacrificial layer44 is silicon dioxide grown using a mixture of oxygen and hydrogen.During formation of sacrificial layer 44, this layer consumes a part ofthe thickness of portion 41 of strained silicon surface layer 18 inregion 30. In an embodiment in which sacrificial layer 44 is silicondioxide, sacrificial layer 44 typically builds up to a thickness T₇ ofslightly more than twice a thickness T₈ of strained silicon surfacelayer 18 that is removed in region 30 by the growth of sacrificial layer44. For example, if strained silicon surface layer 18 has a startingthickness T₄ of 200 Å, and thinned first region 41 of strained siliconsurface layer 18 with an initial thickness T₉ of, for example, 20 Å, isdesired in first region 30, a thickness T₈ of 180 Å of strained siliconsurface layer 18 needs to be removed in first region 30. This strainedsilicon thickness T₈ can be consumed by growing sacrificial layer 44having thickness T₇ of approximately 400 Å.

Referring to FIG. 5 and also to FIG. 6, portion 32 of masking nitridelayer 22 in region 34 is removed by, for example, an RIE process.Subsequently, portion 40 of pad oxide 20 and substantially all ofsacrificial layer 44 are removed with an oxide etch selective tosilicon, such as a hydrofluoric acid etch. The removal of sacrificiallayer 44 exposes thinned first region 41 of strained silicon surfacelayer 18 with initial thickness T₉ disposed over first substrate region30. Thinned strained silicon surface layer first region 41 is proximatea second (unthinned) region 47 of strained silicon surface layer 18 insecond substrate region 34. Initial thickness T₉ of thinned surfacelayer first region 41 is less than starting thickness T₄ of surfacelayer second region 47, which remains substantially unmodified. Initialthickness T₉ is selected to be relatively thin so as to, in a PMOStransistor, facilitate control by a gate voltage of hole transport inSiGe layer 16 and possibly in strained silicon surface layer 18 (see,e.g., PMOS transistor 59 in FIG. 8). Referring still to FIGS. 5 and 6and also to FIG. 7, initial thickness T₉ of strained silicon surfacelayer 18 also has a minimum limit. Strained silicon surface layer 18,including both thinned first region 41 and unthinned second region 47,must be thick enough to enable subsequent growth of a gate dielectric48, such as a gate oxide, having satisfactory integrity. For purposeshereof, a gate oxide with satisfactory integrity is one that has, forexample, a relatively low interface state density, e.g., less than1×10¹¹ eV⁻¹ cm⁻², and/or a relatively low leakage current, e.g., <10nanoamperes/square micrometer (nA/μm²) to 1 microampere/square micron(μA/μm ) or even 10 μA/μm², preferably approximately 10-100 nA/μm² at100° C. In some preferred embodiments, the leakage current may rangefrom approximately 10-100 nA/μm². Thermal oxidation of SiGe ordeposition of oxide films on SiGe results in high interface statedensity (>1×10¹¹−1×10¹² eV⁻¹ cm⁻²). High interface state density at thesemiconductor-insulator interface leads to undesirable shifts inthreshold voltage and in extreme cases unacceptably large subthresholdslope. It is preferable, therefore, to grow gate oxide layers onsilicon, rather than on SiGe. A thin gate oxide layer with satisfactoryintegrity can be grown on strained silicon surface layer 18 having athickness T₉ of approximately 10-20 Å. In an embodiment, strainedsilicon surface layer 18 thickness T₉ is approximately 15 Å. Gate oxide,when grown on silicon, consumes a silicon thickness equal toapproximately one-half of the thickness of the gate oxide grown. Leavinga margin for error, initial thickness T₉ of thinned strained siliconsurface layer 41 can therefore be approximately 15 Å when the desiredgate dielectric thickness is approximately 15 Å. Alternatively, T₉ canbe selected as the final desired thickness, and gate dielectric layer 48can be deposited rather than grown.

A gate dielectric layer 48 is formed on a top surface 50 of strainedsilicon surface layer 18. Gate dielectric layer 48 is, for example, agate oxide with satisfactory integrity having a thickness T₁₀ ofapproximately 10-100 Å. In an embodiment, gate dielectric layer 48thickness T₁₀ is approximately 15 Å. If the initial thickness T₉ ofthinned strained silicon surface layer first region 41 is 15 Å afterremoval of sacrificial layer 44 (see FIGS. 5 and 6), thinned strainedsilicon surface layer 41 has a lower final thickness T₁₁ after growth ofdielectric layer 48; once again, an oxide layer grown on strainedsilicon surface layer 18 typically builds up to a thickness of slightlymore than twice a thickness of strained silicon surface layer 18 that isremoved in region 30 by the growth of the oxide layer. Thinned strainedsilicon surface layer first region 41 final thickness T₁₁ is, forexample, less than 10 Å when gate dielectric layer 48 has a thicknessT₁₀ of approximately 15 Å and thinned strained silicon surface layerfirst region 41 initial thickness T₉ is 15 Å. Second strained siliconsurface layer region 47 is also thinner after gate dielectric layer 48growth. If strained silicon surface layer region 47 initial thickness T₄is 200 Å (see FIG. 1), after growth of gate dielectric layer 48 withthickness T₁₀ of, e.g., 15 Å, strained silicon surface layer region 47final thickness T₁₂ is approximately 192 Å.

Referring to FIG. 8, a conducting layer, such as doped polysilicon, isdeposited over gate dielectric layer 48. The conducting layer ispatterned by, for example, photolithography and etching, to define afirst gate 52 in first region 30 and a second gate 54 in second region34. First gate 52 is, for example, a gate for a PMOS transistor 59 andsecond gate 54 is, for example, a gate for an NMOS transistor 64. Afirst source 56 and a first drain 58 (defined for purposes ofillustration, by the interior boundaries) are formed in first region 30,proximate first gate 52. First source 56 and first drain 58 can beformed by the implantation of p-type ions, such as boron. PMOStransistor 59 includes first source 56, first drain 58, first gate 52and a first dielectric layer portion 48 a. A second source 60 and asecond drain 62 are formed in second region 34, proximate second gate54. Second source 60 and second drain 62 can be formed by theimplantation of n-type ions, such as phosphorus. NMOS transistor 64includes second source 60, second drain 62, second gate 54, and a seconddielectric layer portion 48 b.

During operation of PMOS transistor 59, an operating voltage bias 52 vis applied to first gate 52. The operating voltage 52 v modulates themovement of charge carriers in PMOS transistor 59. More specifically,charge carriers 67, e.g., holes travel through a compressed channel 66in compressed SiGe layer 16 from first source 56 to first drain 58. Thecompressive strain of compressed SiGe layer 16 enhances the mobility ofholes. Final thickness T₁₁ of strained silicon surface layer firstregion 41 is sufficiently small so that the operating voltage 52 vapplied to first gate 52 can modulate the movement of charge carriers 67within compressed SiGe layer 16, and without drawing a majority of thecharge carriers into tensilely strained silicon surface layer firstregion 41 between first source 56 and first drain 58. The majority ofcarriers 67 remain in compressed channel 66 in compressed SiGe layer 16,thereby retaining the benefits of enhanced performance resulting fromgreater carrier mobilities.

During operation of NMOS transistor 64, an operating voltage 54 v isapplied to second gate 54. Charge carriers 67, e.g., electrons travelthrough a strained channel 68 in strained silicon surface layer secondregion 47 from second source 60 to second drain 62. The strain ofsurface layer 18 enhances the mobility of electrons, and final thicknessT₁₂ of strained silicon surface layer second region 47 is sufficientlyhigh to confine the electrons in channel 68.

A dual-channel CMOS device 70 includes PMOS transistor 59 and NMOStransistor 64. In PMOS transistor 58, thinner thickness T₁₁ of strainedsilicon surface layer first region 41 allows modulation of carriers 67,e.g., holes, in compressed channel 66 by bias 52 v applied to first gate52. In adjacent NMOS transistor 64, thicker thickness T₁₂ of strainedsilicon surface layer second region 47 provides an adequate volume forconfinement of carriers 67, e.g. electrons, in strained channel 68.

Referring to FIG. 9, in an embodiment, an alternative layer structure111 is provided on a substrate 100. Substrate 100 is a semiconductor,such as silicon. An insulator layer 120 is disposed over substrate 100.Insulator layer 120 is made of an insulating material such as glass orsilicon dioxide, and has a thickness T₁₃ of, e.g., 500-1500 Å. A relaxedSiGe layer 140 is disposed over insulator layer 120. Relaxed SiGe layer140 contains, for example, 30% Ge and has a thickness T₁₄ of, e.g., 500Å. A compressed SiGe layer 160 is disposed over relaxed SiGe layer 140.Compressed SiGe layer 160 contains, for example, 60% Ge and has athickness T₁₅ within a range of, e.g., 20-200 Å. In an embodiment,compressed SiGe layer 160 thickness T₁₅ is 100 Å. A strained siliconsurface layer 180 is disposed over compressed SiGe layer 160. Strainedsilicon surface layer 180 has a thickness T₁₆ within a range of, forexample, 50-200 Å. In an embodiment, strained silicon surface layer 180thickness T₁₆ is 150 Å. A suitable substrate 100 with layers 111, alsocalled a SiGe-on-insulator (SGOI) substrate, can be produced using acombination of wafer bonding and ultrahigh vacuum chemical vapordeposition, as described, for example, by Cheng, et al., PCT ApplicationNo. PCT/JUS01/41680, International Publication Number WO 02/15244 A2,2002, incorporated herein by reference, and Cheng et al., Journal ofElectronic Materials, Vol. 30, No. 12, 2001, incorporated herein byreference. Relaxed SiGe layer 140 is optional. In an alternativeembodiment, compressed SiGe layer 160 and strained silicon surface layer180 can be provided directly onto insulator layer 120 by, e.g., waferbonding.

Referring to FIG. 10, strained silicon surface layer 180 is selectivelythinned by, e.g., formation of a sacrificial oxide (not shown), asdescribed above with reference to FIGS. 2-6. Strained silicon surfacelayer 180 has a first region 200 with a thickness T₁₇, that is less thana thickness T₁₈ of a second region 210 of strained silicon surface layer180. Substrate 100 with layers 111 is subsequently processed, asdescribed above with reference to FIGS. 7-8, to form, for example, aPMOS transistor (not shown) in first region 220 with thinned strainedsilicon surface layer 200 and an NMOS transistor (not shown) in secondregion 230.

While the invention has been particularly shown and described withreference to specific embodiments, it should be understood by thoseskilled in the art that various changes in form and detail may be madetherein without departing from the spirit and scope of the invention asdefined by the following claims. For example, the describedsemiconductor structures can be fabricated on a substrate without agraded SiGe layer. PMOS well formation can be performed either before orafter patterning of pad oxide and masking nitride layers, either beforeor after the formation of the sacrificial oxide, and either before orafter the removal of the sacrificial oxide. Masking nitride can beremoved by a wet etch, such as by a heated phosphoric acid bath.Strained silicon layer can be selectively thinned by methods other thangrowth of a sacrificial oxide, such as by etching.

It is noted that various processing sequences such as cleaning steps canremove a thickness of exposed strained silicon. The final thickness ofthinned strained silicon surface layer first region and the finalthickness of strained silicon surface layer region may, therefore, beaffected by these additional process steps. These steps can be takeninto consideration when calculating appropriate initial and finalstrained silicon thicknesses to obtain desired final thicknesses afterthe gate dielectric layer is formed.

Gate dielectric can be a material that is deposited, e.g., a high-kdielectric. In this embodiment, the exposed strained silicon layer willnot be consumed during the gate dielectric formation process.

An NMOS device can be formed in a region having a thinner strainedsilicon layer than the strained silicon layer thickness in a regionwhere a PMOS device is formed. First source and first drain can ben-type, and second source and second drain can be p-type. PMOS and NMOSdevices can be fabricated on various alternative substrates, usingmethods described above.

The invention may be embodied in other specific forms without departingfrom the spirit or essential characteristics thereof. The foregoingembodiments are therefore to be considered in all respects illustrativerather than limiting on the invention described herein. Scope of theinvention is thus indicated by the appended claims rather than by theforegoing description, and all changes which come within the meaning andrange of equivalency of the claims are intended to be embraced therein.

1.-24. (canceled)
 25. A method for forming a semiconductor structure,the method comprising the steps of: providing a substrate having asurface layer disposed thereon, the surface layer comprising strainedsilicon; selectively forming a sacrificial layer in a portion of thesurface layer; and substantially removing the sacrificial layer todefine a first region of the surface layer having a first thickness anda second region of the surface layer having a second thickness, whereinthe first thickness is less than the second thickness.
 26. The method ofclaim 25 further comprising: prior to forming the sacrificial layer,forming a masking layer over the surface layer; and removing a portionof the masking layer to expose the portion of the surface layer, whereinthe sacrificial layer is subsequently selectively formed in the portionof the surface layer exposed by the masking layer.
 27. The method ofclaim 26, wherein forming the masking layer comprises forming a maskingsilicon nitride layer.
 28. The method of claim 27, wherein forming themasking layer comprises forming a pad silicon dioxide layer prior toforming the masking silicon nitride layer.
 29. The method of claim 25further comprising: forming a first source and a first drain in thefirst region of the surface layer, the first source and the first drainincluding a first type of dopant; and forming a second source and asecond drain in the second region of the surface layer, the secondsource and the second drain including a second type of dopant.
 30. Themethod of claim 29, wherein the first type of dopant is n-type and thesecond type of dopant is p-type.
 31. The method of claim 29, wherein thefirst type of dopant is p-type and the second type of dopant is n-type.32. The method of claim 25, wherein the surface layer is disposed over arelaxed layer.
 33. The method of claim 32, wherein the relaxed layercomprises germanium.
 34. The method of claim 32, wherein the relaxedlayer comprises silicon.
 35. The method of claim 25, wherein the surfacelayer is disposed over an insulator layer.
 36. The method of claim 25,wherein the surface layer is disposed over a compressively strainedlayer.
 37. The method of claim 36, wherein the compressively strainedlayer comprises SiGe.
 38. The method of claim 36, wherein thecompressively strained layer is disposed over an insulator layer. 39.The method of claim 25 further comprising forming a gate dielectric overthe first and second regions of the surface layer.
 40. The method ofclaim 39, wherein forming the gate dielectric comprises oxidation. 41.The method of claim 39, wherein forming the gate dielectric comprisesdeposition.
 42. The method of claim 41, wherein the gate dielectriccomprises a high-k dielectric.
 43. The method of claim 25, whereinproviding the substrate comprises wafer bonding.